1. Field of the Invention
The present invention relates to a trace control circuit for outputting trace information for use in effectuating a high-efficient program debugging operation, and more particularly relates to a trace control circuit which is preinstalled in a microcomputer and capable of outputting real-time trace information regarding the operation of a CPU.
2. Description of the Related Art
Conventionally, program debugging operations concerning microcomputers have normally been performed by use of an In-Circuit Emulator (hereinafter referred to just as an “ICE emulator”). An ICE emulator has a function of emulating a program debugging operation concerning the microcomputer. In order to realize the emulation by use of an ICE emulator, conventionally address busses and data busses in a microcomputer are first connected to a memory means on an ICE emulator, and a program is downloaded from a host computer controlling the ICE emulator to the memory means of the ICE emulator so as to operate the microcomputer. Thereafter, the program debugging operation is executed regarding a connection terminal on the ICE emulator as being an external terminal of the microcomputer provided in a program-debugging target system.
Normally, in an LSI in which a microcomputer is preinstalled, programs are stored in a memory device preinstalled in the microcomputer, so that the address busses and data busses regarding the CPU of the microcomputer are not connected to the external terminal of the LSI. For this reason, the address busses and data busses have to be drawn to the LSI external terminal by providing an ICE connection exclusive mode, and in this ICE connection exclusive mode, the process concerning the essential function of the LSI external terminal used as a connection terminal for these address busses and data busses is emulated within the ICE.
However, as the connection between the LSI as the target system and the ICE requires the same number of connection terminals as that of the microcomputer, it has become more difficult in recent years to make a connection between the ICE and the target system, due to the fact that the operation speed of the computers are generally made faster, the number of data busses is increased and so on. Further, since a system LSI containing therein a microcomputer is provided with various function elements for realizing various functions of the system in addition to this microcomputer, it has been made more difficult to emulate the essential function of the LSI external terminal used as a connection terminal for these address busses and data busses in the ICE connection exclusive mode.
Due to various factors as mentioned above, it has become more popular nowadays to employ a program developing method for debugging programs, in which a debugging circuit is installed in a microcomputer to replace the function of an ICE emulator, and connected to an external debugger located at the host computer side by way of an LSI terminal exclusively used for debugging operation. FIG. 14 is a block diagram showing the configuration of a microcomputer equipped with a conventional debugging circuit. In this figure, numeral 101 denotes a microcomputer equipped with a conventional debugging circuit, 102 denotes a CPU, 103 denotes a memory, 104 denotes a control bus, 105 denotes an address bus, 106 denotes a data bus, 107 denotes a bus interface, 108 denotes a control bus, 109 denotes an address bus, 110 denotes a data bus, 111 denotes a debugging circuit, 112 denotes a comparator, 113 denotes a download control circuit, 114 denotes a register control circuit, 115 denotes a trace control circuit, 116 denotes a register circuit. Further, numerals 117, 118, 119, 120, 121, 122, 123, and 124 all denote signal lines, reference character “DATA” denotes a multi-bit data signal terminal for inputting and outputting data to and from the external debugger, “CLK” denotes a clock signal terminal through which clock signals for tracing are transmitted for synchronizing with the trace data, “OE” denotes a control signal terminal through which a control signal for controlling input and output of data signals and clock signals, and character “SYNC” denotes a synchronous signal terminal through which a synchronous signal for tracing is transmitted. Input and output of data to and from the debugging circuit can be performed by use of these data signal terminal “DATA”, the clock signal terminal “CLK”, the control signal terminal “OE” and the data signal terminal “SYNC”.
Next, the operation of the above-explained microcomputer equipped with a conventional debugging circuit is now explained below.
First, when a program is formed in the host computer, the host computer executes input and output of data to and from the debugging circuit 111 by use of the externally connected debugger through the data signal terminal “DATA”, the clock signal terminal “CLK” and the control signal terminal “OE”.
The data input to the debugging circuit 111 is decoded at the register control circuit 114, and thereafter reading of data from or outputting of data to each of the comparator 112, the download control circuit 113, the trace control circuit 115 and the register circuit 116 (registers 0 to 3) are performed by way of the signal lines 118, 119 and 120.
Next, by use of an external debugger, the program data formed by the host computer is input to the debugging circuit 111 through the clock signal terminal “CLK”, the data signal terminal “DATA”, and the control signal terminal “OE”. The download control circuit 113 downloads the input program data to the preinstalled memory 103 of the microcomputer 101 through the control bus 104, the address bus 105, and the data bus 106.
Thereafter, the trace control circuit 115 takes in the data transmitted by way of the control bus 108, the address bus 109 and the data bus 110, and outputs trace information regarding the operating state of the CPU 102, by way of the clock signal terminal “CLK”, the data signal terminal “DATA” and the synchronous signal terminal “SYNC”.
Further, the host computer preliminarily writes a predetermined program execution address and a predetermined data into the comparator 112 by way of the clock signal terminal “CLK”, the data signal terminal “DATA” and the control signal terminal “OE”. The comparator 112 monitors the operational state of the CPU, and in a case where the signal data transmitted through the control bus 108, the address bus 109 and the data bus 110 coincides with the previously stored predetermined program execution address and the predetermined data, it outputs an interrupt request signal to the CPU 10 by way of the signal line 117. In this case, the CPU 102 executes an interrupt processing program preliminarily downloaded into the memory 103, and performs data communications regarding the interrupt processing between the CPU 102 and the external debugger by way of the register circuit 116.
By performing the above-explained operations concerning the microcomputer 101, the program debugging based on such procedures as shown below are made possible:
1) Make a debugging program by the host computer,
2) Download the program data into the memory preinstalled in the microcomputer
3) Execute the debugging program, triggered by an instruction of the host computer, and grasp the operational state of the microcomputer on the basis of the trace data output from the debugging circuit, and
4) Generate an interrupt request signal when a program address or the like previously set by the host computer appears, and perform data communications between the host computer and the debugging circuit regarding the interrupt processing by way of the external debugger, so as to grasp the operational state of the microcomputer as a whole.
However, in recent system LSIs, a microcomputer installed therein has been made to operate of higher speed, and thus the instruction execution frequency per predetermined time is also made higher, whereby it is made more difficult that the microcomputer extracts trace information from a limited number of connection terminals. FIG. 15 is a block diagram showing the inner construction of the trace control circuit 115 shown in FIG. 14, focussing on the circuit portion related to a generation of branch events. In the trace control circuit of this example, the length of address data is 16 bits, and the length of data to be processed is also 16 bits. In FIG. 15, numeral 131 denotes a branch event generation circuit, 132 denotes a CPU-access event generation circuit, 133 denotes a selector, 134 denotes a trace memory, 135 denotes a trace data output circuit, 136 denotes an OR gate, 137 denotes a status information generation circuit, 138 denotes an address data latch circuit for latching 16-bit data, 139 denotes an AND gate, 140 denotes an address data latch circuit for latching 16-bit data, 141 denotes an AND gate, 142 denotes a buffer, and 143 denotes an AND gate.
Next, the operation of the above-mentioned trace control circuit is explained.
FIG. 16 is a timing chart showing the waveshapes of various signals related to the trace control circuit. In FIG. 16, reference characters P1 and P2 denote base clock signals of the CPU, OPC denotes an ope-code fetch signal, OPCBUS denotes an output data to the ope-code bus, OPR denotes an operand fetch signal, OPRBUS denotes an output data to the operand bus, SYNC_CPU denotes a synchronous signal, RCLR denotes a branch-destination signal, ADCPU denotes an output data to the address bus, BRAS_CLK denotes a branch-source address latch signal, BRAD_CLK denotes a branch-destination address latch signal, SELL denotes a selection signal, TRW1 denotes a write signal to the trace memory 134, CLK denotes a clock signal for tracing, SYNC denotes a synchronous signal for tracing, and DATA denotes a trace data output from the data signal terminal.
As shown in FIG. 16, when the branch-source address latching signal BRAS_CLK which is provided from the AND gate 139 as an ANDed value of the synchronous signal SYNC_CPU and the base clock signal P1 becomes H level, the branch-source address data output to the address bus ADCPU of the CPU is latched by the latch circuit 138. Thereafter, when the branch-destination address latch signal BRAS_CLK, which is provided from the AND gate 141 as an ANDed value of the branch-destination signal RCLR and the base clock signal P1, becomes H level, the branch-destination address data output to the address bus ADCPU of the CPU is latched by the latch circuit 140. Then, when the selection signal SEL1 delayed by the buffer 142 for one base clock cycle with respect to the branch-destination signal RCLR becomes H level, the selector 133 receives data of 36 bits in total; namely 4-bit status information indicating the type of the trace event concerning the CPU output from the status information generation circuit 137, 16-bit branch-source address data output from the latch circuit 138, and 16-bit branch-destination address data output from the latch circuit 140, and selects the signals to be output therefrom. Thereafter, when the write signal TRW1 provided from the AND gate 143 as an ANDed signal of the selection signal SEL1 and the base clock P1 becomes H level, 36-bit data composed of the status information, the branch-source address data and the branch-destination address data is stored in the trace memory 134. Then, when the synchronous signal SYNC for tracing becomes H level, the trace data output circuit 135 synchronizes with the clock CLK for tracing, and reads out the trace data from the trace memory 134, and sequentially outputs the trace data from the data signal terminal “DATA” per every 4 bits. Various data are output from the data signal terminal “DATA” in the order of status information ST, branch-source address (ASHH, ASHL, ASLH, ASLL), and branch-destination address (ADHH, ADHL, ADLH, ADLL). In other words, trace data related to the branch event in response to a branch instruction is output in 9 CLK cycles from the 4-bit data signal terminal “DATA”. It is to be noted that each of the symbols attached to the above addresses; namely HH, HL, LH, and LL means the location of data within the entire 16-bit data, wherein the data location is shifted from the uppermost 4-bit string HH to the lowermost 4-bit string in the order of HH, HL, LH, and LL.
FIG. 17 is a block diagram showing the inner construction of the trace control circuit 115 shown in FIG. 14, focussing on the circuit portion related to generation of the CPU access event. In FIG. 17, the same reference numerals as those in FIG. 15 indicate same or similar portions, so that the detailed explanation thereabout is omitted here. In this trace control circuit also, length of address data is 16 bits, and the length of address data is also 16 bits. In FIG. 17, numeral 151 denotes a status information generation circuit, 152 denotes a selector, 153 denotes an address data latch circuit for latching 16-bit address data, 154 denotes an AND gate, 155 denotes a read or write data latch circuit for latching 16-bit read or write data, 156 denotes an AND gate, 157, 158, 159 and 160 all denote latch circuits for latching 1-bit data and numeral 161 denotes an AND gate.
Next, the operation of the above-mentioned trace circuit is now explained as below.
FIG. 18 is a timing chart showing the waveshapes of various signals regarding the trace control circuit. In FIG. 18, the same reference numerals as those in FIG. 16 indicate same or similar portions, so that the detailed explanation thereabout is omitted here. Reference character RDA denotes a data access request signal from the CPU, DB denotes an output data to the data bus, AD_CLK denotes an address latching signal, DT_CLK denotes a data latch signal, SEL2 denotes a selection signal, TRW2 denotes a write signal into the trace memory 134. As shown in FIG. 18, when the address latch signal AD_CLK, which is provided from the AND gate 154 as an ANDed signal of the data access request signal RDA and the base clock P1, becomes H level, the address data output to the address bus ADCPU of the CPU is latched by the latch circuit 153. Then, when the data latch signal DT_CLK becomes H level, wherein the data latch signal DT_CLK is provided as an ANDED signal of the base clock P1 and the data access request signal RDA which is delayed for 1 base clock signal cycle by the latch circuits 157 and 158 on the basis of the operation of the AND gate 156, the read or write data output to the data bus DB is latched by the latch circuit 155. Thereafter, when the selection signal SEL2 becomes H level, which selection signal being delayed for 2 clock signal cycles with respect to the data access request signal RDA by the latch circuits 157, 158, 159 and 160, the selector 133 receives 36-bit data in total; namely 4-bit status information output from the status information generation circuit 151, 16-bit address data output from the latch circuit 153, and 16-bit read or write data output from the latch circuit 155, and selects the signals to be output therefrom. Then, when the write signal TRW2 provided from the AND gate 161 as an ANDed signal of the selection signal SEL2 and the base clock signal P1 becomes H level, those 36-bit data composed of the status information, address data, and read or write data are stored in the trace memory 134. Thereafter, when the synchronous signal SYNC for tracing becomes H level, the trace data output circuit 135 synchronizes with the clock signal CLK for tracing, and reads out the trace data from the trace memory 134, and sequentially outputs the trace data per every 4 bits. Various data are output from the data signal terminal “DATA” in the order of the status information ST, the address data (AHH, AHL, ALH, ALL), and the read or write data (DHH, DHL, DLH, DLL). In other words, the trace data related to the CPU-access event is output in 9 CLK cycles from the 4-bit data signal terminal “DATA” in response to a data access instruction.
Since a microcomputer carrying a conventional decoding circuit therein is configured as such, there has been such a problem that when the number of address busses and/or data busses is increased, or an instruction execution cycle is shortened, the number of trace busses should be increased, or the frequency of trace-use clock signal should be made higher, in a case where the real-time operation of the CPU is required.